Department of ECE

Mr. Y Sreenivasula Goud, Professor

Overview:

Mr. Y Sreenivasula Goud is currently a Professor in the Department of Electronics and Communication Engineering at Ravindra College of Engineering for Women, Kurnool. He has about 25 years of experience in teaching. He has published research papers in journals of both international and national repute and has also presented many papers in international and national conferences. He holds an M.Tech degree from JNTUA, Anantapur, and has submitted a Ph.D. thesis on “Power Minimization and Test Time Reduction in VLSI Circuits” to JNTUH, Hyderabad. His areas of interest include low power VLSI.

Qualifications:

  • M.Tech (DSCE) from JNTUA, Anantapur in 2006
  • M.S (Software Systems) from BITS (off campus), Pilani, Rajasthan in 2000
  • B.E (ECE) from Osmania University, Hyderabad in 1993

Subjects Taught:

  • Electronics Devices and Circuits
  • Electronic Circuits and Analysis
  • Linear Integrated Circuits Analysis
  • Control Systems
  • Radar Engineering
  • Communication Systems
  • Satellite Communication
  • VLSI Design
  • Constitution of India
  • Design for Innovative Thinking

Publications and Achievements:

List of Journals:

  1. Presented a paper on “Benchmarking models of low power VLSI Testing Strategies: current state of the art” in Global Journal of Researches in Engineering (GJRE), Year 2013, Vol. 13, Issue 7, pp. 5-22, IF 4.135.
  2. Presented a paper on “An optimal swarm intelligence approach for test sequence restructuring to conserve power usage in VLSI testing” in International Journal of Computer Trends and Technology (IJCTT), Oct 2013, Vol. 4, Issue 10, pp. 3693-3696, IF 0.596.
  3. Presented a paper on “Testing of digital circuits with conserved power utilization: jumbled test sequence approach” in IJSER, March-2014, Vol. 5, Issue 3, pp. 896-899, IF 4.2.
  4. Presented a paper on “An intelligence approach to test pattern optimization in digital circuit testing” in International Journal of Advanced Computing, January 2016, Vol. 49, Issue 1, pp. 1-8, IF 3.135.
  5. Presented a paper on “A Novel Clock Divided Address Generator with Hamming Encoder for Implementing the LFSR for Low Power Memory BIST Applications” in International Journal of Control Theory & Applications, 2016, Vol. 31, Issue 9, pp. 1-9, IF 2.56.
  6. Presented a paper on “Transition control modeling for fast fault testing in DFT application” in International Journal of Trend in Research and Development (IJTRD),Dec-2017, special issue, pp. 533-537, IF 4.865.
  7. Presented a paper on “Test power optimization with redundant transition test patterns in Digital Circuit” in IOSR Journal of Electronics and Communication Engineering (UGC approved), (May-June 2018), Vol. 13, Issue 3, pp. 1-8, IF 3.12.
  8. Presented a paper on “Multi Attribute Test Pattern Optimization for Test Power Minimization in Digital Circuits” in International Journal of Innovative Technology and Exploring Engineering (IJITEE) (Scopus), March 2019, Vol. 8, Issue 4S2, pp. 233-236, IF 5.54.
  9. Presented a paper on “Test pattern optimization and test time reduction using probabilistic state control modeling in DFT” in PENSEE International Journal (Scopus), April-2021, Vol. 51, Issue 4, pp. 627-635.
  10. Presented a paper on “Optimizing test time reduction and low power design in fault testing for DFT application” in Gravida Review Journal, Vol. 8, Issue 5, May-2022.
  11. Presented a paper on “A novel approach to layout design of 2-bit binary ripple carry adder using CMOS NAND Gates” in IJIRCCE, Vol. 8, Issue 5, May-2020.
  12. Presented a paper on “Low power and energy-efficient logic circuit design by using adiabatic techniques” in IJIRCCE, Vol. 8, Issue 5, May-2020.

List of Publications in Conferences:

  1. Presented a paper on “Optimal testing approach for low power fault testing in VLSI circuitry” at the International Conference on Innovations in Information, Embedded and Communication Systems (ICIIECS-2017), Karpagam College of Engineering, Coimbatore, March 17th & 18th, 2017, Volume 5.
  2. Presented a paper on “A Novel Block Switch Logic For State-Skip Test Pattern Generation In Built-In Self Test Scheme” at the International Conference on Research Advancements in Engineering, Science, and Information Technology (ICRAESIT-2015), B.V.Raju Institute of Technology, Narsapur, Medak-Dt, December 15th & 16th, 2015.
  3. Presented a paper on “SOLDIER HEALTH AND POSITION TRACKING SYSTEM” at the International Conference on Emerging Trends in Electronics & Communication Engineering (ICETEC-2023), RGM College of Engineering & Technology, Nandyal, Kurnool-Dt, April 15th to 17th, 2023.

Achievements:

  1. Life member of the Indian Society for Technical Education.
  2. Guided several projects for B.Tech and M.Tech students.
  3. Organized technical workshops and seminars.