Department of ECE

Dr. N. Geetha Rani

M.Tech, PhD
Associate Professor
Department of ECE

Dr. N. GEETHA RANI is working as Associate Professor in the Department of Electronics and Communication Engineering at RCEW. She has 14 years of teaching experience. She has obtained Ph.D degree in NANO SCIENCE AND TECHNOLOGY from JNTUH, Hyderabad. She has obtained his Master degree in NANO TECHNOLOGY from JNTUH, Hyderabad. She has obtained his bachelor’s degree in Electronics and Communication Engineering from St Johns College of Engineering and Technology Yemmiganur, JNTUH. Before joining RCEW, she has worked in G Pullaiah College of Engineering and Technology Kurnool, and Stanley Stephen College of Engineering and Technology, Kurnool. Her areas of research are NANO ELECTRONICS. She is a member of Institute of Electrical and Electronics Engineers (IEEE).

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  • PhD (ECE) from JNTUH, Hyderabad
  • M.Tech (ECE) from JNTUH, Hyderabad
  • B.TECH (ECE) from JNTUH, Hyderabad
      • N.Geetha Rani, Dr.P.Chandrasekhar Reddy “A Novel Approach to Enhance Performance in Near-Threshold Logic” International Journal of Nanotechnology and Applications ISSN 0973-631X Volume 10, Number 1 (2016), pp. 1-5. © Research India Publications.
      • N.Geetha Rani, Dr.P.Chandrasekhar Reddy “Ultra Low Power Circuit Design” Science-Direct Materials Today: Proceedings 2 (2015) 4468 – 4473, Available online at www.sciencedirect.com.
      • N.Geetha Rani, Dr.P.Chandrasekhar Reddy “Implementation of Near-Threshold gates at 45nm Technology” International Journal of Applied Engineering Research ISSN 0973-4562 Volume 10, Number 18 (2015) pp 39416-39421 © Research India Publications.
      • N.Geetha Rani, Dr.P.Chandrasekhar Reddy “Design of Memory Cell for Low Power Applications” International Journal of Engineering Research and Applications www.ijera.com ISSN: 2248-9622, Vol. 5, Issue 8, (Part – 1) August 2015.
      • N. Praveen Kumar, N. Geetha Rani, Dr. P. Chandrasekhar Reddy, Dr. B. Stephen Charles “A Low Leakage, High Performance SRAM Cell using 0.18μm Technology” International Journal of Applied Engineering Research ISSN 0973-4562 Volume 6, Number 18 (2011) pp. 2111-2121© Research India Publications. www.ripublication.com/ijaer.htm
      • N. Praveen Kumar, N. Geetha Rani, Dr. P. Chandrasekhar Reddy, Dr. B. Stephen Charles “ASIC Design for Low Power Applications” International Journal of Electronic and Communication Research, ISSN 2231-1246 Volume 2, Number 1 (2011), pp. 55-67© Research India Publications.
      • N. Praveen Kumar, N. Geetha Rani, Dr. P. Chandrasekhar Reddy, Dr. B. Stephen Charles “Design of Near-Threshold CMOS Logic Gates” International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.2, April 2012. DOI: 10.5121/vlsic.2012.3216.
      • N. Geetha Rani, G. Ragapriya, Harshitha V, G. Swetha, B. Sri Jyothi “Leakage Current Reduction in CMOS Circuits Using Stacking Technique” International Journal of Scientific Research in Science, Engineering and Technology (www.ijsrset.com) © 2020 IJSRSET | Volume 7 | Issue 3 | Print ISSN: 2395-1990. DOI: https://doi.org/10.32628/IJSRSET207344.
      • N. Geetha Rani, N. Jyothi, P. Leelavathi, P. Deepthi Swarupa Rani, S. Reshma “Robust 12T Sram Cell Using 45nm Technology” International Journal of Scientific Research in Science, Engineering and Technology (www.ijsrset.com) © 2020 IJSRSET | Volume 7 | Issue 3 | Print ISSN: 2395-1990. DOI: https://doi.org/10.32628/IJSRSET207344.
      • N. Geetha Rani, C. Soundarya Lahari, G. Revathi, K. Chandrika, G. Riya “Minimization of Leakage Currents in Dram 4×4 Using SVL Technique” International Journal of Scientific Research in Science, Engineering and Technology (www.ijsrset.com) © 2020 IJSRSET | Print ISSN: 2395-1990. DOI: https://doi.org/10.32628/IJSRSET218435.
      • N. Geetha Rani, Shaik Noor e Kausar, Tazaeen Sundus, Munagala Vineela, “8 Point DIT-FFT Algorithm Using Verilog” Journal of Switching Hub, Volume-6, Issue-2 (May-August, 2021), (www.matjournals.com). https://doi.org/10.46610/JoSH.2021.v06i02.002.
      • N. Geetha Rani, Shaik Noor e Kausar, Tazaeen Sundus, Munagala Vineela, “Mist Removal Using Fast Algorithm Based on Linear Operator” International Journal of Scientific Research in Science, Engineering and Technology, Volume 9, Issue 2 (March-April-2022). DOI: https://doi.org/10.32628/IJSRSET229263.
      • N. Geetha Rani, Shaik Noor e Kausar, Tazaeen Sundus, Munagala Vineela, “Frequency upon Image Enhancement by using Transform” International Journal of Scientific Research in Science, Engineering and Technology, Volume 9, Issue 2 (March-April-2022). DOI: https://doi.org/10.32628/IJSRSET.
      • N. Geetha Rani “An all optical 2×1 multiplexer using a MetalInsulator-Metal based plasmonic waveguide for processing at a rapid pace”, Manuscript ID: photonics-2050800.
      • N. Geetha Rani “Design of Graphene Nano ribbon FET using Quantum wise ATK”, Advanced Engineering Sciences. Volume 54, Issue 8, Publication Issue: OCT 2022. ISSN: 2096-3246.
  • N.Geetha Rani, Dr.P.Chandrasekhar Reddy “Ultra Low Power Circuit Design” at the International Conference on Nano Science & Engineering Applications (ICONSEA-2014), CNST, IST JNTUH, held on 26-28th June 2014. ISBN NO: 978-81-924726-2-1.
  • N.Geetha Rani “Leakage Power Reduction Techniques for Memory Cell At 45nm Technology With Increased Threshold Voltage” at the International Conference on Advanced Communications, VLSI and Signal Processing (ICACVSP-2015), on April 11th, 2015.
  • N.Geetha Rani, Dr.P.Chandrasekhar Reddy “Design of Near-Threshold CMOS Logic Gates for Nano-Scale Electronic Systems” at the National Conference on Nano Science & Engineering Applications (NCONSEA-2014), CNST, IST JNTUH, held on 27-28th April 2012. ISBN NO:978-81-924726-0-7.
  • N.Geetha Rani, Dr.P.Chandrasekhar Reddy “A Low Leakage, High Performance SRAM Cell using 0.18μm Technology” at the International Conference on Soft Computing and Engineering Application (ICSEA-2011), Kolkata, held on 11 Sep 2011.
  • N.Geetha Rani, Dr.P.Chandrasekhar Reddy “Performance Enhancement of Sub-threshold Circuits using Gate Level Body Bias Technique” at the National E-Conference On Technology for Impactful and Sustainable Development of the Society (TISDS-2020), December 15-16, 2020.
  • Patent- Application Number- 202241071383, “A NOVEL STRUCTURE FOR CONTROLLING DEGRADATION OF TRANSIENT ELECTRONICS” – applied on 07-Mar-2022 – PUBLISHED on 6th day of December 2022.
  • Indian Patent- Application Number- 202241034402, “Bike Helmet Crash Sensors using IOT” – applied on 07-Mar-2022 – PUBLISHED on 24-06-2022.
  • Indian Patent- Application Number- 202041025847, “DESIGN OF AUTONOMOUS ROBOTS USED TO DISINFECT HOSPITAL ROOMS WITH CONCENTRATED UV LIGHT” – applied on 19-July-2020 – PUBLISHED on 10-07-2020.