Prof Y.Sreenivasulu Goud
B.Tech., M.Tech(Ph.D), MISTE
Professor and Head
Email-Id:hodece@recw.ac.in
Contact:9951860531

Y.Sreenivasula Goud is working as Professor in the Department of Electronics &Communication Engineering at RCEW.. He has 22 years of teaching and perusing Ph.D at JNTUH,Hyd. He has obtained his masters degree in Digital systems and computer electronics from JNTUA, Anantapur in the year 2006. He has obtained his bachelor’s degree in Electronics &communication engineering from the MVSR Engineering College, Osmania University, Hyderabad in the year 1993. His areas of research are low power VLSI. He is a member of Indian Society for Technical Education .He has published 10 papers in reputed international journals &coferences.He has guided 6 PG and 30 UG projects. He has worked in the following institutions: G.Pulla Reddy Engineering College, Kurnool,AP  Kottam College of Engineering, Kurnool G.Pullaiah College of Engineering &Technology,Kurnool

  1. VLSI DESIGN.
  2. VHDL PROGRAMMING.
  3. CONTROL SYSTEMS.
  4. LINEAR INTEGRATED CIRCUIT APPLICATIONS.
  5. ELECTRONIC MEASUREMENT & INSTRUMENTATION.
  6. COMMUNICATION SYSTEMS.
  7. ELECTRONIC DEVICES & CIRCUITS.
  8. ANALOG ELECTRONIC CIRCUITS.

PAPER PUBLISHED:-

  1. Design and implementation of simultaneous shield and repeater insertion for on chip interconnects, IJECE, Volume 3, Issue 1, Jan-2012
  2. Bench marking models of low power VLSI Testing Strategies:: current state of art,GJRE,Volume13,Issue7,2013
  3. An optimal swarm intelligence approach for test sequence restructuring to conserve power usage in vlsi testing, IJCTT, Volume4, issue10, oct 2013
  4. Testing of digital circuits with conserved power utilization: jumbled test sequence approach, IJSER, Volume 5, issue 3,Mar-14
  5. A novel Block switch Logic For State-Skip Pattern Test Pattern Generation in Built in Self Test Scheme, IARJSET, Volume 2, issue 2,Dec-2015
  6. An intelligence Approach to Test Pattern Optimization in digital Circuit Testing, International Journal of advanced Computing, volume49, issue 1, January-2016
  7. A Novel Clock Divided Address Generator with Hamming Encoder for Implementing the LFSR for Low Power Memory BIST Applications, International journal of control theory &applications( Scopus),December-2016
  8. Transition control modeling for fast fault testing in DFT application in IJTRD , ISSN: 2394-9333, www.ijtrd.com
  9. Test power optimization with redundant transition test patterns in digital circuit,IOSR journal of ECE,ISSN:2278-8735,volume-13,Issue-3,(May-June,2018),PP 01-08
  10. Published a paper Entitled “Multi attribute test power optimization for test power minimization in Digital  circuits” in IJITEE,ISSN 2278-3075,Volume-8,issue 4S2-March-2019

 

WORKSHOPS ATTENDED:

  1. Participated in the Short term course on “Improving teaching skills ”. from 16.3.2004 to 18.3.2004 by NITTTR at GPREC
  2. Attended a two day workshop on “Lab view and Virtual instrumentation” from 9th-10th dec-2004 at GPREC
  3. Attended a three day workshop on “Functional Approach to VLSI design &Technology” from 12th-14th feb-2007 at GNITS,Hyd
  4. Participated in workshop on”Overview of VLSI –CAD tools “from 17th &18th august 2007 at NIT,Trichy
  5. Attended a training programe on “Instructional Strategies “in association with NITTTR,from july 27th to 29th ,2008 at GPREC
  6. Participated a workshop on “VLSI Design”held from Feb 13-14,2009 at SKTRMCE
  7. Participated a workshop on “Microstrip antenna “held on 10th jan 2014 at GPCET
  8. Participated in training programe on “Formulations of Reserch &development initiatives for engineering faculty by ESCI on 28th &29th july 2014 at GPCET
  9. Participated in the Faculty Development Programme on “Embedded Linux & Application Development Using ARM9”.on 11th &12th july 2014 at GPCET
  10. Participated in the Faculty Development Programme on “signal processing using MATLAB”on 20th december2014 at GPCET
  11. Participated one day FDP on “Outcome Based education ”  held on 10th december -2015 at GPREC
  12. Participated one week FDP on “Cadence tools ”  held on 12th december -2017 at GPCET
  13. Participated Three days FDP on “IUCEE international Educator pre- certification Workshop  held ofrom  Feb 8-10,2018 at GPCET
  14. Participated Two day FDP on “Designing experiments with Analog Discovery Kit”held on 14th &15th April ,2018 at GPCET

 

SEMINARS/ CONFERENCES ATTENDED:

  1. Presented a Paper Entitled “A novel Block switch Logic For State-Skip Pattern Test Pattern Generation in Built in Self Test Scheme” in Internal Conference ,BVRIT,Hyd,held during 15th &16th Dec-2015
  2. Presented a paper on “Digital water marking based on sphit coding “in national conference(NCRTEC-2007 on 25th January 2007,GPREC
  3. Participated one day seminar on “Quality practices in technical education –Challenges “organized by ISTE faculty chapter of GPCET on 28th December 2015
  4. Participated in one day seminar on “research topics and methodologies in VLSI & Embedded Appliction “ “organized by Unistrings Tech solutions (UTS) pvt.ltd on 20th sep-2014 at Hyd
  5. Presented a Paper Entitled “Optimal testing approach for low power fault testing in vlsi circuitry”in Internal Conference , Iciiecs-2017, karpagam college of engg.,Coimbatoor,IEEE Madras section,held during 17th &18th Mar-2017
  6. Presented a Paper Entitled “Transition control modeling for fast fault testing in DFT
    1. Application” in Internal Conference , RIET-2017,GPREC,Kurnool, Dec 15th &16th,2017
  7. Presented a Paper Entitled “Optimal testing approach for low power fault testing in vlsi circuitry” in ICIIECS 2017,Karpagam college of Engineering in association with IEEE Madrass section during 17th and 18th march 2017
  8. Presented a paper Entitled “Multi attribute test power optimization for test power minimization in Digital circuits” in ICSPECS-2019,GPREC,Kurnool

RESEARCH AREA : VLSI TESTING.