G.Sivaiah 
B.Tech., M.Tech.,MISTE.,MIMES.
Assistant Professor 

G.SIVAIAH is working as Assistant Professor in the Department of Electronics and Communication Engineering. He has a 11 years 4 months of teaching experience. He is qualified in UGCNET 2017 for Assistant Professor. He has obtained his Master of Technology in VLSI System Design from Jawaharlal Nehru Technological University, Ananthapur in the year 2008. He has obtained his Bachelors degree in Electronics and Communication Engineering from the Vardhaman College of Engineering (VCE), Shamshabad, Jawaharlal Nehru Technological University, Hyderabad in the year 2006. His areas of research are VLSI and Digital Design. He is a member of Indian Society for Technical Education (MISTE) and Institute for Mathematicians Engineers and Scientists (MIMES). He has published 5 papers in reputed international journals. He has guided 6 PG and 14 UG projects

  1. EMBEDDED SYSTEMS.
  2. ELECTRONIC DESIGN AUTOMATION TOOLS.
  3. DIGITAL DESIGN THROUGH VERILOG HDL.
  4. PULSE & DIGITAL CIRCUITS.
  5. LOW POWER VLSI.
  6. ANALOG IC DESIGN.
  7. SATELLITE COMMUNICATION.
  8. DIGITAL SYSTEM DESIGN.
  9. OPTICAL FIBER COMMUNICATION .
  10. RF INTEGRATED CIRCUITS.

PAPER PUBLISHED:-

  1. Zipper Circuit for Low Power and High Speed Applications in VLSI Design, IJSRD, Vol. 6, Issue 12, 2019 | ISSN (online): 2321-0613
  2. Digital low drop-out regulator with coarse-fine dual loop in mobile application processor with a 200-mA, IJTRD,ISSN:2394-9333,Dec 2017
  3. Design of  digital logic with 3T technique for high speed and low power applications in VLSI Design, IJTRD,ISSN:2394-9333,Dec 2017
  4. A Comparator Circuit Design Using Cyclic Combinational Gate Diffusion Input(CCGDI) - For Low Power ,Low area and High speed applications in VLSI Design in, IJIRCCE, Volume 4,Issue 7, July 2016

  5. Impact of hybrid pass transistor logic(HPTL) on Power, delay and area in VLSI Design”, IJMER, Vol.4, Issue 6, June 2014

WORKSHOPS ATTENDED:

  1. Participated in the one day work shop on “Fuzzy Control”, held at SVPCET,Puttur on 7th march 2009. SVPCET, Puttur

  2. Participated in the one day work shop on “Is world united at Copenhagen to combat climate change”, held on 2nd feb 2010 , SVPCET, Puttur

  3. Participated in the one day work shop on “Reconfigurable technologies and its applications”,       at Anna University   held on 18 december 2011. Anna University ,Chennai.

  4. Participated in the one day work shop on “Signal and Image Processing using MATLAB”, under ISTE  Faculty Chapter held on 20 december 2014, GPCET, Kurnool.

  5. Participated in the one day national level work shop on “Latest issues in microstrip antennas”, under ISTE  Faculty Chapter held on 10 jan 2014, GPCET, Kurnool.

  6. Participated in the two day national level work shop on “VLSI Circuits Design using Mentor graphics tools”, under ISTE  Faculty Chapter held on 13&14 march 2015, SEC, Nandyal.

  7. Participated in the two day work shop on outcome based education on 26th and27th Nov 2016, GPCET, Kurnool

FACULTY DEVELOPMENT PROGRAMS:

  1. Participated in MeitY,Govt of India Sponsered one week  FDP on “Real Time Embedded Systems and IoT its applications” from 1st- 6th may 2017, GPCET,KURNOOL.
  2. Certificate of  Achievement for successful completion of an NILab VIEW Core 1 & Core 2” course from 22nd - 26th may 2017, GPCET,KURNOOL.
  3. Participated a two day FDP on “Design&simulation of antennasµwave devices using HFSS Tool” on 5th and 6th December 2015, GPCET,KURNOOL.
  4. Participated a one day seminar on “Quality practices in technical education-challenges” on 29th December 2015, GPCET,KURNOOL.

SEMINARS/ CONFERENCES ATTENDED:

  1. G.Sivaiah "VLSI Implementation of Precoding matrix Generation System for MIMO Wireless Channels”, Emerging Trends in Engineering National Conference, on 16th -17th April,2008, SVPCET,PUTTUR.

  2. G.Sivaiah "FPGA Implementation of FIFO Based Multi Channel UART controller for Complex Control Systems”, National Conference on Network Technologies,29th DEC ,2009. SVPCET,PUTTUR.

  3. G.Sivaiah” High Speed Parallel Architecture for Cyclic Convolution Based on ENT” National Conference on Recent Trends in Electronics & Communication Engineering on 8th Dec 2010. SIETK,PUTTUR.

  4. Participated in the two day national level Conference on “recent trends in electronics and communication engineering”, held on 8&9 march 2010.

 

 

VLSI System Design